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Si3480
3. Functional Description
3.1. Device Initialization and Configuration Pins
The Si3480 will discover Si3452 devices at addresses 0x20 and 0x21 at power up. If only one device is found, it
will manage the power for four ports. If two devices are found, the Si3480 will manage power for eight ports. For the
case of eight ports, ports 1–4 are associated with the Si3452 at address 0x20, and ports 5–8 are associated with
device 0x21. After power-up, the CFG pins are measured to determine how power is to be managed.
3.1.1. Pin PWRCFG
The voltage on pin PWRCFG specifies the power provided by the system power supply. The power provided is:
P PROVIDED = 200 x V PWRCFG / V DD (Watts)
The total power provided is the rating of the main power supply for continuous output. The amount of total power
provided depends on the expected usage. 30 W of total power provided might be realistic for a four-port system
that only supports 15.4 W per port and is not expected to have PDs on all ports. 150 W of total power might be
realistic for an eight port system that supports 30 W per port and is expected to have category 2 PDs connected to
all ports.
To avoid overloads, a port will not be granted power unless the power consumed plus the power requested
according to classification (4, 7, 15.4, or 30 W) allows for 15% power supply reserve. If, due to variation in power
over time, the total power consumed by all the loads exceeds the power supply capacity, the power manager will
shut down ports in priority order.
3.1.2. Pin POECFG
The voltage on the POECFG pins determines how many ports are enabled for 30 W maximum per port. If the
voltage is at ground, no ports will be enabled for 30 W maximum. If the voltage is at V DD , all ports are enabled for
30 W maximum. The number of ports enabled for 30 W is:
N = 8 x V POECFG / V DD rounded to the nearest integer
In a four-port system, V POECFG > V DD / 2 means that 30 W is enabled on all ports.
If a port is enabled for 30 W maximum, special high-current Ethernet transformers should be used, and the user
should be aware that the wiring to the PD should be category 5E or better or category 5 manufactured after 1995
(See 802.3 clause 33 for details).
3.1.3. Pin PRIOCFG
The Si3452 implements a port priority set according to the voltage on pin PRIOCFG. Low priority ports may be
turned off if a high priority port is requesting power. Also, low-priority ports are shut down before high-priority ports
in case the power supply is overloaded. Similar to the POECFG pin, the number of ports that are high priority is:
N = 8 x V PRIORITYCFG / V DD rounded to the nearest integer
3.1.4. Pin ALTCFG
The Si3480 can be set to put the Si3452 parts in either Alternative A or Alternative B timing mode. Alternative A is
used when the power is applied to wire pairs 1,2 and 3,6. Alternative B is used when the power is applied to wire
pairs 4,5 and 7,8. Timing between detection pulses is less than 0.5 s for Alternative A and greater than two
seconds for Alternative B. The timing is Alternative A if pin ALTCFG is tied low and Alternative B if the pin is tied
high.
3.2. I 2 C Communication
The open drain Si3480 pins (SDA, SCL, and INT) are for I 2 C communication and connect to the Si3452/53 pins
with the same name. See the Si3452/53 data sheet for more detailed information.
3.3. LED Control
The LED pins each connect to two LEDs. The LED being driven is determined by the LEDBANK pin in a normal
multiplexing fashion. The LEDBANK pin is driven at 500 Hz (1 msec high and 1 ms low).
6
Rev. 1.0
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